This invention relates to a semiconductor device for inputting and outputting a signal in synchronism with a high-speed clock signal, and more particularly, to a clock signal processing circuit and method and a semiconductor device wherein a clock signal is processed in an improved method, which are effectively used in a synchronous DRAM (Dynamic Random Access Memory).
With an increase in the operational speed of a MPU (Micro Processing Unit), an increase in the operational speed of a semiconductor memory is being required. In the case of the synchronous DRAM operable in synchronism with a clock signal, for example, data transfer at a high speed cycle of 100-200 MHz is needed.
Further, with an increase in memory capacity from 64 M-bits to 256 M-bits, the memory chip size is increased. Accordingly, when an external clock signal is taken and used as an internal clock signal, the internal clock signal may be delayed, depending upon which portion of the memory chip receives the signal.